Title :
A structured approach to macrocell testing using built-in self-test
Author_Institution :
AT&T Bell Lab., Princeton, NJ, USA
Abstract :
The proposed design-for-testability strategy suggests first dividing a complex VLSI system into various structural modules and then implementing a specific built-in self-test (BIST) scheme for each module. A general procedure to realize BIST in a specific set of modules, namely the macrocells is described. The availability of the automated BIST for macrocells has increased the ease of testing for embedded macrocells, standardized macrocell testing for embedded macrocells, standardized macrocell testing strategy, almost eliminated the test vector generation time for these structures, reduced the diagnostic runtimes, decreased the overall chip cost, and decreased the turn-around time to get the devices to market
Keywords :
VLSI; built-in self test; logic testing; modules; BIST; VLSI system; built-in self-test; design-for-testability strategy; diagnostic runtimes; macrocell testing; overall chip cost; standardized macrocell testing; structural modules; structured approach; test vector generation time; turn-around time; Automatic testing; Built-in self-test; Circuit faults; Design for testability; Logic; Macrocell networks; Read only memory; Registers; System testing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124820
