Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm

Full-adders are used extensively in most types of digital computing systems. Any design decision made at the full-adder level is likely to have a significant impact on the speed or power consumption of the entire digital system. In this paper, we study how various full-adder topologies are affected by the Gated-V_dd and Gated-V_ss techniques at 65 nm and 45 nm, from a leakage power-delay perspective. We observed that most of the circuits studied resulted in leakage-current savings of more than 80% with Gated-V_dd, incurring a small delay penalty. Delay penalty in case of Gated-V_dd is more that of Gated-V_ss. In Gated-V_ss, there is a wide variation in leakage power between the topologies studied.