A second-order gate delay modeling method with an efficient sensitivity analysis

As CMOS technology scales, to consider process variation becomes increasingly challenging. Statistical gate delay model is widely used technique to analyze the influence of process variation on gate delay. We propose a second-order gate delay model which is more accurate even with the larger variance of variations. The number of additional variables introduced by second-order terms is minimized using sensitivities and statistically combined variables. The runtime cost to calculate sensitivity values is reduced by simplifying the process to determine worst-case and best-case parameters. The accuracy of the model is verified by experiments on a gate, inverter-chain, and a circuit. Comparing to Monte Carlo simulation, the mean and standard deviation obtained by the proposed model have average error rates of 1.26% and 4.31%, respectively. We present the error reduction rate of the proposed model, compared to the first-order model. The average error reduction rate is 36.7%.