The APx accelerator

Author

Abreu, E. ; Jenkins, D. ; Hervin, M. ; Evans, D.

Author_Institution

Visionary Syst. Inc., New Haven, CT, USA

fYear

1988

fDate

10-12 Oct 1988

Firstpage

413

Lastpage

417

Abstract

The architectural and implementational features that work together in the APx accelerator to achieve high sustained system performance for a significant set of compute-intensive functions are presented. The features include VLSI integration, memory bandwidth, concurrency of operations, interprocessor communications, processor selection mechanisms, and I/O bandwidth. The APx is an expandable system and provides from 64 to 256 16-bit processors which provide peak instruction rates from 800 to 3200 MIPs. The individual processors in the APx accelerator are 16-bit RISC processors which are quite powerful and versatile. In addition, pairs of 16-bit processors can be configured to operate in 32-bit mode under software control. IEEE format single precision floating-point operations are supported in 32-bit mode with peak ratings from 40 to 160 MFLOPS

Keywords

parallel architectures; parallel machines; satellite computers; 16 bit; 16-bit RISC processors; 32 bit; 40 to 160 MFLOPS; 800 to 3200 MIPS; APx accelerator; I/O bandwidth; VLSI integration; compute-intensive functions; interprocessor communications; memory bandwidth; processor selection mechanisms; system performance; Acceleration; Bandwidth; Computer architecture; Concurrent computing; Parallel processing; Process design; Reduced instruction set computing; Supercomputers; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Frontiers of Massively Parallel Computation, 1988. Proceedings., 2nd Symposium on the Frontiers of

Conference_Location

Fairfax, VA

Print_ISBN

0-8186-5892-4

Type

conf

DOI

10.1109/FMPC.1988.47462

Filename

47462