The design and algorithm mapping of a heterogeneous multi-core processor for SDR

In this paper, we present a new fully programmable heterogeneous multi-core processor architecture for SDR (software defined radio). To meet the computation properties of different algorithms, our solution contains three types of processor cores: two SIMD (Single Instruction Multiple Data) cores, four general purpose DSP cores and an embedded controller core. In order to verify the efficiency of our processor architecture, we implement baseband algorithms of W-CDMA (Wideband Code Division Multiple Access) and WiMax (Worldwide Interoperability for Microwave Access), and mapped them onto the proposed architecture. The result exhibits that this solution can support W-CDMA and WiMAX at about 25.7 mm² and 0.47 W at 70 nm technology.