Title :
A test strategy for a bit-serial VLSI chip with analog I/O
Author_Institution :
David Sarnoff Res. Center Inc., Princeton, NJ, USA
Abstract :
A unique, one-bit-wide test bus was designed to assure random pattern testability of a bit-serial stereo signal processor chip with analog I/O. Analog circuitry was tested functionally and digital circuitry pseudorandomly, achieving very high fault coverage. Analysis of fault simulation results indicates better than 99.9% coverage of the datapath logic was achieved. These results were obtained from an approximate fault simulator that neglects the possibility of fault self-masking caused by reconvergent fanout. The use of this tool in particular cases is justified by circuit analysis using fault path (F-path) methods
Keywords :
VLSI; analogue-digital conversion; digital signal processing chips; fault location; integrated circuit testing; logic testing; F-path methods; analog I/O; bit-serial VLSI chip; circuit analysis; datapath logic; fault coverage; fault self-masking; fault simulation; functional testing; pseudorandom testing; random pattern testability; reconvergent fanout; stereo signal processor chip; test strategy; Circuit faults; Circuit testing; Clocks; Inspection; Logic devices; Logic testing; Sequential analysis; Signal design; Signal processing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124824
