Title :
Boolean minimization using new ATPG techniques and saved test patterns
Author :
Morrison, Christopher
Author_Institution :
VLSI Technol., Valbonne, France
Abstract :
An enhanced approach to the Boolean minimization of a combinational logic circuit is described. The approach uses random automatic test pattern generation (ATPG) and recent developments in deterministic ATPG techniques, and reuses saved test patterns to eliminate additional calls to RATPG and DATPG. Modifications to a previous approach are presented, as well as the enhancements to the new DATPG method. The resulting minimization program can solve problems that the previous method could not, and can solve others up to 2000 times faster
Keywords :
automatic testing; combinatorial circuits; logic testing; minimisation of switching nets; ATPG techniques; Boolean minimization; combinational logic circuit; deterministic ATPG; random automatic test pattern generation; saved test patterns; Automatic test pattern generation; Automatic testing; Boolean functions; Circuit testing; Combinational circuits; Cost function; Logic testing; Minimization methods; Test pattern generators; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124826
