Robust solution for synchronous communication among multi clock domains

The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications do not guarantee dependability for all data, especially when different clock domains are interconnected. In this paper we propose to take advantage of these approaches, by combining, the robustness of asynchronous communication and the speed and simplicity of synchronous communications. A structure has been developed to implement the proposed communication approach. A test chip has been designed to implement that structure and prove the concept. The usefulness of the methodology is demonstrated in a complex FPGA data acquisition system. Simulation results are presented.