Exploring the design space in high-level synthesis

A versatile scheduling algorithm has been developed as part of the BRIDGE synthesis system. This algorithm schedules the various operations in the given sequential behavioral description into a designer-specified number of control steps. Scheduling is performed by computing the attraction forces for each operation to each control step. A novel concept of sharing forces is used to increase multifunction functional unit utilization. These sharing forces are determined by performing look-ahead on functional unit allocation. With the scheduler, the designer can systematically explore the design space by controlling the number of control steps. Estimates of operation delay times are used to drive the synthesis. Experimental results were obtained by synthesizing the entire design all the way to the gate level and measuring the transistor count (to approximate area) and by measuring the critical path delay using a timing analyzer. Results show an increase in functional unit utilization because of the sharing forces used. The results also show that the size of the controller and the path delay in the controller cannot be ignored in exploring design trade-offs. Some other interesting results are reported