Self-organizing map hardware accelerator system and its application to realtime image enlargement

Author

Tamukoh, Hakaru ; Aso, Takashi ; Horio, Keiichi ; Yamakawa, Takeshi

Author_Institution

Graduate Sch. of Life Sci. & Syst. Eng., Kyushu Inst. of Technol., Japan

Volume

4

fYear

2004

fDate

25-29 July 2004

Firstpage

2683

Abstract

We propose a new fast learning algorithm for SOM and its digital hardware design based on the massively parallel architecture. When this proposed algorithm is realized by using Xilinx XC2V6000-6 FPGA, a maximum performance of 17500 MCUPS is achieved and up to 256 competing units (16 × 16 map) can be implemented. Each competing unit have a weight vector which is represented by 128 elements of 16 bits accuracy. Furthermore, we applied the proposed hardware to a realtime digital image enlargement system. In the case of full color (24 bits) image enlargement from QQVGA (160 × 120 pixel) to QVGA (320 × 240 pixel), a proposed hardware requires only 0.12 second per image, while the personal computer (Intel XEON, 2.8 GHz Dual) requires more than 5 seconds per image.

Keywords

field programmable gate arrays; image processing; learning (artificial intelligence); self-organising feature maps; Xilinx XC2V6000-6 FPGA; digital hardware design; fast learning algorithm; realtime image enlargement; self-organizing map hardware accelerator system; Algorithm design and analysis; Circuits; Design engineering; Digital images; Electronic mail; Engineering management; Hardware; High performance computing; Pixel; Technology management;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on

ISSN

1098-7576

Print_ISBN

0-7803-8359-1

Type

conf

DOI

10.1109/IJCNN.2004.1381073

Filename

1381073