On output reorder buffer design of bit reversed pipelined continuous data FFT architecture

Fast Fourier transform (FFT) is the reduced complexity algorithm to implement highly computational complex discrete Fourier transform (DFT). Cooley-Tookey based decomposition method is the most popular technique for an N point DFT where N is an integral power of 2. There are 2 decomposition techniques, decimation in frequency (DIF) and decimation in time (DIT), which are widely popular. Both the techniques require a core design and either an output reorder section or an input reorder section depending on whether we are using DIF or DIT respectively. An extensive literature is available for the core design part. However we donpsilat find much literature which discussed the design issues of the reorder section. Moreover if the design is targeted for high throughput application and incoming data is continuous in nature it becomes a challenging problem to design the reorder section with minimum complexity. In this paper we formulate the minimum latency required to reorder output (or input) of a DIF (or DIT) FFT architecture of N point, where N is an integer power of 2. We also find out the minimum buffer length required to implement the reorder section. Finally we propose a simple low power reorder architecture using a single random access memory (RAM) suitable for continuous data, pipelined FFT architecture. The proposed architecture is more valuable for high value of N.