Title :
Circuit partitioning and resynthesis
Author :
Dey, Sujit ; Brglez, Franc ; Kedem, Gershon
Author_Institution :
Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
Abstract :
A circuit partitioning method based on analysis of reconvergent fanout is introduced. A DAG model for a circuit is considered. A corolla is defined as a set of overlapping reconvergent fanout regions. The DAG is partitioned into a set of nonoverlapping corollas, and the corollas are used to resynthesize the circuit. It is shown that resynthesis of large benchmark circuits consistently reduces transistor pairs and layout area, while improving delay and testability
Keywords :
circuit layout CAD; directed graphs; integrated logic circuits; logic CAD; DAG model; circuit partitioning method; corolla; delay reduction; layout area reduction; reconvergent fanout; reduces transistor pairs; resynthesis of large benchmark circuits; set of nonoverlapping corollas; set of overlapping reconvergent fanout regions; testability improvement; Automatic testing; Benchmark testing; Circuit synthesis; Circuit testing; Combinational circuits; Logic circuits; Logic testing; Partitioning algorithms; Programmable logic arrays; Signal analysis;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124829
