A CMOS low-voltage fully differential sample-and-hold circuit

A new technique for realizing a CMOS low-voltage fully differential sample-and-hold circuit is presented. A low-voltage technique is proposed for CMOS sample-and-hold circuit that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. For 2.5 MHz input signal frequency, the proposed sample-and-hold circuit exhibits a THD of -62 dB for 1.0 V_pp input signal at 25 MHz sampling rate. Simulation results are given to demonstrate the potential advantage of the new technique.