Design of a bridge to randomly access high speed image sensor pixels in embedded systems

Most commercially available image sensors send image data at high speed and pixel values can only be accessed sequentially. Random access of pixels is not possible because pixel values are sent row-after-row. On the other hand, commercial microcontrollers run at slower speed compared to the high data-rate of the image sensors and many embedded system applications need random access of pixel values. Also, commercial microcontrollers do not have sufficient internal memory to store a complete image. In this paper, the design of a novel bridge is proposed to interface high speed image sensors in low power and low speed embedded systems. By using the proposed bridge, the image processor or microcontroller can capture and store an image in the bridge´s internal memory. Then the pixel values can be accessed in random fashion through a parallel memory access interface at any required speed. The bridge can be used in different embedded system applications such as pattern recognition, robotic vision, bio-medical imaging etc. The proposed bridge was modelled in Very-high-speed integrated circuit Hardware Description Language (VHDL) and implemented in Field Programmable Gate Array (FPGA) to verify its correctness. The model was also synthesized in different FPGA devices and result shows that the bridge can support data-rate of image sensors up to 252.1 MHz in Xilinx Vertex 5 FPGA.