DocumentCode
2327904
Title
Design of quaternary serial and parallel adders
Author
Das, Anindya ; Jahangir, Ifat ; Hasan, Masud
Author_Institution
Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
fYear
2010
fDate
18-20 Dec. 2010
Firstpage
466
Lastpage
469
Abstract
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel using mathematical expressions.
Keywords
adders; adder circuits; binary logic system; chip area; full adder; gate delay; logarithmic stage parallel adder; optimization technique; quaternary logic system; quaternary serial adder; Logarithmic stage adder; Quaternary fast adder; Quaternary full adder; Ripple carry adder;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering (ICECE), 2010 International Conference on
Conference_Location
Dhaka
Print_ISBN
978-1-4244-6277-3
Type
conf
DOI
10.1109/ICELCE.2010.5700730
Filename
5700730
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