DocumentCode
2327940
Title
Developing parallel architectures for range and image sensors
Author
Guo, Shaori ; Luk, Wayne ; Probert, Penelope
Author_Institution
Dept. of Eng. Sci., Oxford Univ., UK
fYear
1994
fDate
8-13 May 1994
Firstpage
2205
Abstract
We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic implementation using field-programmable gate arrays (FPGAs) are presented. Experiments and analyses indicate that our circuits can satisfy the performance requirements, and some of the designs out-perform the software equivalent on a 486-based PC by nearly two orders of magnitude
Keywords
distance measurement; edge detection; field programmable gate arrays; image processing; image processing equipment; image sensors; programmable logic arrays; systolic arrays; 486-based PC; FPGA; field-programmable gate arrays; image sensors; parallel architecture development; parametrised edge detector; range sensors; systolic implementation; Circuits; Detectors; Field programmable gate arrays; Image edge detection; Image sensors; Parallel architectures; Performance analysis; Sensor arrays; Software design; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Robotics and Automation, 1994. Proceedings., 1994 IEEE International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-8186-5330-2
Type
conf
DOI
10.1109/ROBOT.1994.350957
Filename
350957
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