Title :
A 0.8V SOP-based cascade multibit delta-sigma modulator for wideband applications
Author :
Kuo, Chien-Hung ; Lee, Kuan-Yi ; Chen, Shuo-Chau
Author_Institution :
Dept. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
In this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.
Keywords :
CMOS integrated circuits; cascade networks; operational amplifiers; sigma-delta modulation; wideband amplifiers; SOP-based cascade multibit delta-sigma modulator; fourth-order DeltaSigma modulator; integrator path; low-distortion topology; power 15.7 mW; signal-to-noise plus distortion ratio; switched-opamp; voltage 0.8 V; wideband applications; CMOS technology; Clocks; Delta modulation; Distortion; Dynamic range; Energy consumption; Quantization; Sampling methods; Topology; Wideband;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746247