A simple RISC microprocessor core designed for digital set-top-box applications

We propose the definition and evaluation of an instruction set designed and tuned for multimedia applications on a digital set-top-box. The proposed instruction set had its performance evaluated in software and hardware to obtain the best cost/benefit relationship referring to performance and silicon chip area. An instruction set was obtained enhancing the performance of iDCT algorithms to achieve the needs of real time MPEG-2 video decompression and to have an extra processing power available for future more complex algorithms (e.g., MPEG-4). A RISC basic core was modeled in VHDL and the defined instruction set was added into this core. In this way, the evaluations were made through out logical simulations by implementing over FPGAs, and the results of the added instructions over the algorithm performance were evaluated using high-level synthesis tools and infield tests