Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA

The network on chips (NoCs) is a promising solution for future on-chip interconnection. In this area, fast and accurate performance evaluation and design space exploration for the NoCs are critical issues. In this paper, we design a NoC prototype which consists of 4 ARM compatible cores and a router-based on-chip network, and implement it on a FPGA device. The performances of this prototype are evaluated under two real applications. Specially, we compare the performance of NoC architecture with which of hierarchy shared-bus and point-to-point architecture. The results show that the NoC architecture provides the best performance of speedup ratio with moderate area overhead.