The design and transport latency analysis of a locality-aware network on chip architecture

The major drawback of an on-chip network is the strongly decreased timing predictability due to the dynamic routing. While for some special applications, such as distributed shared memory (DSM) and multi-mode cryptosystems, itpsilas not necessary to introduce the dynamic routing mechanism between multiple processing elements (PEs) due to their different communication features. Therefore, we propose a hierarchical topology which is scalable, resource-efficient, latency-predictable, compact and easy to implement due to its simple interconnect. In a hierarchical topology, the router can be designed statically so that the transport latency of packets transmitted via the on-chip network becomes much easier to predict as long as the deadlock and starvation problems have been prevented. In this paper, we analyze the local transport latency and the global transport latency of our application specific NoC design and show that they are predictable and bounded within a boundary derived from the proposed prediction equations.