Title :
High level synthesis for peak power minimization using ILP
Author :
Tsong Shiue, Wen
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Abstract :
The work presented in this paper focuses on behavioral level power optimization. Specifically, we address the problem of scheduling a data-flow graph under latency constraints. We have developed an integer linear program (ILP) model and a Modified Force-Directed Scheduling (MFDS) that minimize the peak power while satisfying timing constraints. Our integer linear programming method extends the traditional ILP approach that minimizes resources to include peak power consideration while adding extensions for multi-cycle and pipelined arithmetic components. In our benchmark results, the peak power is reduced after scheduling based on ILP method and MFDS algorithm and is reduced significantly after scheduling and pipelining are both applied. The results obtained by the heuristic-based algorithms (MFDS) match very well with those obtained by the integer linear programming (ILP) methods. While the results obtained by heuristic-based algorithm are approximate, the results obtained by the integer linear programming methods are optimal. But the heuristic-based algorithm is faster than the integer linear programming methods
Keywords :
circuit CAD; circuit optimisation; data flow graphs; high level synthesis; integer programming; integrated circuit design; linear programming; low-power electronics; minimisation; pipeline arithmetic; scheduling; timing; DFG scheduling; HLS; ILP model; behavioral level power optimization; data-flow grap; heuristic-based algorithms; high level synthesis; integer linear program model; integer linear programming method; latency constraints; modified force-directed scheduling; multi-cycle arithmetic components; peak power minimization; pipelined arithmetic components; pipelining; timing constraints; Circuits; Delay; Energy consumption; High level synthesis; Integer linear programming; Low power electronics; Registers; Throughput; Timing; Voltage;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-0716-6
DOI :
10.1109/ASAP.2000.862382