DocumentCode :
2328457
Title :
Cost effective hardware sharing architecture for fast 1-D 8×8 forward and inverse integer transforms of H.264/AVC high profile
Author :
Su, Guo-An ; Fan, Chih-Peng
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung
fYear :
2008
fDate :
Nov. 30 2008-Dec. 3 2008
Firstpage :
1332
Lastpage :
1335
Abstract :
In this paper, the fast one-dimensional (1-D) 8times8 integer transforms and the sharing design for 1-D 8 times 8 forward and inverse integer transforms of H.264/AVC are proposed by using the matrix operations, which are the row/column permutations, the decompositions with the sparse matrices, and the matrix offset computations. The computational complexities of the proposed fast 1-D 8times8 forward integer transform of H.264/AVC is the same as those of the previous fast methods. By using the proposed fast algorithms with the sharing hardware, the proposed sharing implementation requires lower hardware cost than the individual and separate design for the VLSI realization.
Keywords :
VLSI; matrix algebra; transforms; video coding; H.264/AVC; VLSI realization; computational complexities; cost effective hardware sharing; integer transforms; matrix offset computations; sparse matrices; Algorithm design and analysis; Automatic voltage control; Computational complexity; Costs; Hardware; Matrix decomposition; Sparse matrices; Symmetric matrices; Very large scale integration; Video coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
Type :
conf
DOI :
10.1109/APCCAS.2008.4746274
Filename :
4746274
Link To Document :
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