Title :
Generation of scheduling functions supporting LSGP-partitioning
Author_Institution :
Dept. of Electr. Eng., Tech. Univ. Dresden, Germany
Abstract :
In this paper we present an approach to determine scheduling functions suitable for the design of processor arrays. The considered scheduling functions support a followed LSGP-partitioning of the processor array by allowing to execute the tasks of processors of the full-size array mapped into one processor of the partitioned processor array in an arbitrary order. Several constraints are derived to ensure the causality of computations and to prevent access conflicts to both modules and registers. We propose an optimization problem generating the scheduling functions and outline its implementation as an integer linear program. The proposed methods are also applicable for the mapping of algorithms to parallel architectures. In this case, the scheduling function produces identical, independent small threads which can be combined to utilize the target architecture as much as possible
Keywords :
high level synthesis; integer programming; linear programming; microprocessor chips; multiprocessing systems; parallel architectures; processor scheduling; LSGP-partitioning; integer linear program; optimization problem; parallel architectures; partitioned processor array; processor arrays; scheduling functions generation; Algorithm design and analysis; Delay; Electrical capacitance tomography; Equations; Iterative algorithms; Multiprocessing systems; Process design; Processor scheduling; Registers; Yarn;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-0716-6
DOI :
10.1109/ASAP.2000.862405