Title :
High level synthesis techniques for efficient built-in-self-repair
Author :
Guerra, Lisa M. ; Potkonjak, Miodrag M. ; Rabaey, Jan M.
Author_Institution :
Dept. of EECS, California Univ, Berkeley, CA, USA
Abstract :
Built-in-self-repair (BISR) is a hardware redundancy fault tolerance technique, where a set of spare modules is provided in addition to core operational modules. Until now, the application of BISR methodology has been limited to situations where a failed module of one type can only be replaced by a backup module of the same type. It is shown that in ASIC designs it is possible to enable replacement of modules of different types with the same spare units by exploiting the flexibility of high level synthesis solutions. Resource allocation, assignment and scheduling techniques that support a new BISR methodology are presented. All mentioned high level synthesis algorithms are developed on top of the HYPER high level synthesis system, using a novel statistical methodology for heuristic algorithm development and improvement. The effectiveness of the approach is verified and yield improvement data is presented for numerous real-life examples
Keywords :
redundancy; ASIC designs; BISR methodology; HYPER high level synthesis; VLSI; assignment; efficient built-in-self-repair; hardware redundancy fault tolerance technique; heuristic algorithm development; high level synthesis; replacement of modules; scheduling; statistical methodology; yield improvement data; Application specific integrated circuits; Fault tolerance; Fault tolerant systems; Hardware; High level synthesis; Laboratories; National electric code; Random access memory; Redundancy; Space exploration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice
Print_ISBN :
0-8186-3502-9
DOI :
10.1109/DFTVS.1993.595623
