Efficient designs of flaoting-point CORDIC rotation and vectoring operations

Two processor designs are presented that can compute CORDIC rotation and vectoring operations in floating-point representation. In order to achieve the required accuracy, we partition the computation into two phases: coarse and fine, and look for efficient design approaches to minimize the area cost as well as the latency. The proposed architectures can perform floating-point CORDIC in both vectoring and rotation modes, allowing them to be applied to applications that require high accuracy arithmetic computations with large data ranges, such as 3D graphics acceleration.