DocumentCode
2328894
Title
An interactive/automatic floor planner for hierarchically designed cell based VLSIs
Author
Hiwatashi, Tamotau ; Kurosawa, Sachiko
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1990
fDate
13-16 May 1990
Abstract
A floor planner suitable for hierarchically designed cell-based VLSIs to achieve an optimum layout design is described. The proposed floor planner has two novel features: the first is the combination of both manual manipulation in floor planning and automatic floor planning in order to make the best use of each method, considering the interdependence of these two methods. The second is the introduction of a novel concept to handle the hierarchical structure of a design in the floor planning stage. The floor planner used the simulated annealing algorithm in the heuristic of the iterative improvement stage of the automatic floor planning
Keywords
VLSI; cellular arrays; circuit layout CAD; automatic floor planning; combined manual automatic layout design; features; hierarchical structure; hierarchically designed cell based VLSIs; interactive/automatic floor planner; iterative improvement stage; module generation; optimum layout design; simulated annealing algorithm; Design automation; Design engineering; Design optimization; Iterative methods; Logic design; Process planning; Routing; Simulated annealing; Ultra large scale integration; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/CICC.1990.124836
Filename
124836
Link To Document