Design of high-performance transform and quantization circuit for unified video CODEC

This paper presents the new high-performance circuit architecture of the transform and quantization for unified video CODEC. The proposed architecture can be applied to all kinds of transforms for the video compression standards such as JPEG, MPEG-1/2/4, H.264 and VC-1. It exploits the similarity of 4-point DCT and 8-point DCT using permutation matrices. Since our circuit accepts the transform coefficients from the users, it can be extended very easily to cover any kind of DCT-based transforms for future standards. The multipliers in the transform circuit are shared by the quantization circuit in order to minimize the circuit size. The quantization operations are performed using spare clock cycles during the transform operations in order to minimize the number of clock cycles required. We described the proposed transform circuit at RTL and verified its operation on FPGA board.