Title :
Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems
Author :
Tajalli, Armin ; Leblebici, Yusuf
Author_Institution :
Microelectron. Syst. Lab. (LSM), Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
Abstract :
The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access memory (SRAM) array has been implemented to demonstrate the performance of this topology for ultra-low-power consumption and low-activity-rate digital circuits. A novel 9 T memory cell has been developed to reduce the stand-by (leakage) current to 10 pA/cell while the SRAM array is operating at 2.1 MHz clock frequency. The power consumption benefits of the proposed circuit style can be maintained in nanometer CMOS technology nodes.
Keywords :
CMOS memory circuits; SRAM chips; leakage currents; low-power electronics; CMOS circuits; low activity rate digital systems; source coupled logic power efficiency; static random access memory; subthreshold leakage consumption; ultra low power SRAM; CMOS logic circuits; CMOS memory circuits; CMOS technology; Circuit topology; Digital circuits; Digital systems; Energy consumption; Logic circuits; Random access memory; Subthreshold current;
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4354-3
DOI :
10.1109/ESSCIRC.2009.5325939
