A yield centric statistical design method for optimization of the SRAM active column

Author

Doorn, T.S. ; Croon, J.A. ; Maten, E. J W Ter ; Bucchianico, A. Di

Author_Institution

NXP Semicond., Eindhoven, Netherlands

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

352

Lastpage

355

Abstract

For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization of the access time of an SRAM memory, while guaranteeing a yield target set by the designer. Using this method, the access time of a high performance advanced CMOS SRAM has been improved 6%, while simultaneously reducing the sense amplifier size.

Keywords

CMOS memory circuits; SRAM chips; amplifiers; circuit optimisation; integrated circuit design; statistical analysis; SRAM active column optimization; SRAM cell parameters; SRAM memories robust design; high performance advanced CMOS SRAM; sense amplifier size reduction; yield centric statistical design method; Design methodology; Design optimization; Optimization methods; Probability; Random access memory; Robustness; Statistical analysis; Stochastic processes; System performance; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5325954

Filename

5325954