DocumentCode
2329520
Title
Defect Reduction Using Yield Management Test Structures
Author
Chou, H.M. ; Liu, C.C. ; Kuo, C.J. ; Hwang, J.H. ; Wu, N.W. ; Chang, M.C.
Author_Institution
ERSO Sub-uM Fab, ITRI
fYear
1994
fDate
21-22 June 1994
Firstpage
147
Lastpage
150
Abstract
Design and applications of Yield Management test patterns on memory products have been reviewed. Evaluations are made for Y.M. patterns and conventional T.K. patterns in terms of their ability to faithfully point out process deviations/defects and to predict CP yield. It s assessed that Y.M. patterns are superior to T.K. patterns in terms of the previous criteria. Finally, design guidelines will be also discussed.
Keywords
Chemical processes; Costs; Guidelines; Inspection; Manufacturing; Memory management; Polymers; Probes; Testing; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 1994. Extended Abstracts of ISSM '94. 1994 International Symposium on
Conference_Location
Tokyo, Japan
Type
conf
DOI
10.1109/ISSM.1994.729442
Filename
729442
Link To Document