DocumentCode
2329989
Title
Application Of A Graph Description Method For Structural And Electrical Analysis Of VLSIs
Author
Ochiai, Katsuyuki ; Tazawa, Satoshi ; Nakajima, Shigeru
Author_Institution
NTT LSI Laboratories
fYear
1994
fDate
21-22 June 1994
Firstpage
221
Lastpage
222
Abstract
A graph description method is proposed to describe layout pattern data. The Graph can express not only pattern positions but also physical attributes of the patterns. Therefore, the data processing time for structural recognition of LSI is less than a method dealing with pattern data of vertex coordinates directly.
Keywords
Capacitance; Data processing; Failure analysis; Information analysis; Laboratories; Large scale integration; Pattern analysis; Pattern recognition; Scanning electron microscopy; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 1994. Extended Abstracts of ISSM '94. 1994 International Symposium on
Conference_Location
Tokyo, Japan
Type
conf
DOI
10.1109/ISSM.1994.729463
Filename
729463
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