VLSI implementation and optimization design of Reed-Solomon decoder in QAM demodulation chip

Based on time-domain modified Berlekamp-Massey (BM) algorithm, a Reed-Solomon (RS (204,188)) decoder under the DVB-C standard is designed optimally. New pipeline architecture is adopted in this decoder. In addition, finite-field constant multipliers and specially the time-division-multiplex structure used for key equation solution are proposed, which reduce the bulk of circuit and simplify the complexity of the hardware architecture. The RS decoder has been synthesized with design compiler and SMIC 0.18 mum CMOS technology and the implementation result shows a scale of about 22159 gates. At most 8 bytes errors for each data frame (204 Bytes) under the demanded working frequency of 30 MHz can be detected and corrected, which meets the performance required in QAM demodulation chip.