Timing-driven multi-layer Steiner tree construction with obstacle avoidance

Given a set of connecting nodes in a signal net with a set of obstacles on different layers for 3D ICs, based on the refinement of minimum routing region and the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree with obstacle avoidance. Compared with a spanning-tree-based approach, the experimental results show that our proposed approach has 9.7%~17.3% improvement in timing delay for the tested examples in reasonable CPU time.