DocumentCode
2330189
Title
Gate sizing by lagrangian relaxation revisited
Author
Wang, Jia ; Das, Debasish ; Zhou, Hai
Author_Institution
Northwestern Univ., Evanston
fYear
2007
fDate
4-8 Nov. 2007
Firstpage
111
Lastpage
118
Abstract
In this paper, we formulate the generalized convex sizing (GCS) problem that unifies and generalizes the sizing problems. We revisit the approach to solve the sizing problem by Lagrangian relaxation, point out several misunderstandings in the previous works, and extend the approach to handle general convex delay functions in the GCS problems. We identify a class of proper GCS problems whose objective functions in the simplified dual problem are differentiable and show many practical sizing problems, including the simultaneous sizing and clock skew optimization problem, are proper. We design an algorithm based on the method of feasible directions to solve proper GCS problems. The algorithm will provide evidences for infeasible GCS problems according to a condition derived by us. Experimental results confirm the efficiency and the effectiveness of our algorithm when the Elmore delay model is used.
Keywords
convex programming; delays; logic circuits; logic gates; Elmore delay model; clock skew optimization; convex delay functions; gate sizing; generalized convex sizing; lagrangian relaxation; Algorithm design and analysis; Circuits; Clocks; Computer science; Delay effects; Design optimization; Lagrangian functions; Timing; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-1381-2
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2007.4397252
Filename
4397252
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