DocumentCode
2330274
Title
NXG05-1: Interleaved Multistage Switching Fabrics for Scalable High Performance Routers
Author
He, Rongsen ; Delgado-Frias, Jose G.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA
fYear
2006
fDate
Nov. 27 2006-Dec. 1 2006
Firstpage
1
Lastpage
5
Abstract
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay latency and good reliability. At present, most of these routers and switches are implemented on single crossbar as the switched backplane fabric. But the complexity of the single crossbar is increased with O(N2 ) in terms of crosspoint number, which is unacceptable for scalability when N becomes large. A delta class self-routing multistage interconnection network with the complexity of O(Ntimeslog2N) has been widely used in the ATM switches. However, the reduction of the crosspoint number results in the serious internal blocking. To solve this problem, quite a few scalable methods have been proposed. One of them, more stages with recirculation architecture is used to reroute the deflected packets, which increase the latency a lot. In this paper, we first bring out the multiple-panel MIN switching fabrics with interleaved recirculation. We also show how to correctly choose the recirculation points to reroute the cells, compared with the wrong connections of former publication. From the simulation under different traffic patterns, this new interleaved architecture, which is insensitive to congestion, could achieve better performance than its counterpart of single panel fabric.
Keywords
asynchronous transfer mode; communication complexity; multistage interconnection networks; network routing; ATM switches; crossbar complexity; delta class self-routing multistage interconnection network; interleaved multistage switching fabrics; interleaved recirculation; multiple-panel MIN switching fabrics; scalable high performance routers; scalable high performance switches; Asynchronous transfer mode; Backplanes; Delay; Fabrics; Internet; Multiprocessor interconnection networks; Scalability; Spine; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE
Conference_Location
San Francisco, CA
ISSN
1930-529X
Print_ISBN
1-4244-0356-1
Electronic_ISBN
1930-529X
Type
conf
DOI
10.1109/GLOCOM.2006.341
Filename
4150971
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