647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA

Author

Devlin, Benjamin ; MyeongGyu, J. ; Nakura, Toru ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

156

Lastpage

159

Abstract

We propose a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to eliminate pre-charge time for dynamic logic. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bit SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers. One common block with one SSLUT and one SSSB occupies 2.2lambda² area and the prototype SSFPGA with 34 times 30 (1020) blocks is designed and fabricated using 65 nm CMOS. Measured results show 647 MHz operation for a chain of 32 AND gates at 1.2 V and 430 MHz operation for a 3 bit ripple carry adder. Simulation results show 0.642 pJ/block/cycle operation at 647 MHz, 1.2 V.

Keywords

CMOS logic circuits; SRAM chips; UHF integrated circuits; adders; buffer circuits; field programmable gate arrays; logic gates; table lookup; 3 bit ripple carry adder; 8 bit SRAM; AND gates; CMOS; SSFPGA; SSLUT; SSSB; buffers; dual-pipeline architecture; dynamic logic; frequency 430 MHz; frequency 647 MHz; pass transistors; pre-charge time; self synchronous LUT; self synchronous field programmable gate array; self synchronous switch box; three input tree-type structure; voltage 1.2 V; Circuits; Design engineering; Educational programs; Field programmable gate arrays; Pipelines; Programmable logic arrays; Rails; Robustness; Switches; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5326010

Filename

5326010