Synthesis of VHDL code for FPGA design flow using Xilinx PlanAhead tool

This paper addresses a synthesis process of VHDL code for FPGA design flow using Xilinx PlanAhead tool. This tool provide a low power profile, more hard IP functionality, create a global timing constraint, lower node capacitance & architectural innovations, cost of development, very high DSP performance hardware solutions and easily can be evolutionary algorithms, reconfigured to the development of whole compiler, simulation and synthesis frameworks. It is handle dense logic and memory elements offering very high logic capacity. The logic blocks are replicated in FPGA with interconnects and input-output blocks. This approach attached a new created VHDL code and generate of register-transfer level (RTL) hardware description language (HDL). In this paper, we have presented the FPGA approach of interconnection and its flexibility on example through synthesis process, simulations and implemented results are detailed.