A 1-V 84-dB DR 1-MHz bandwidth cascade 3–1 Delta-Sigma ADC in 65-nm CMOS

Author

Cornelissens, Koen ; Steyaert, Michiel

Author_Institution

ESAT-MICAS, K.U. Leuven, Leuven, Belgium

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

332

Lastpage

335

Abstract

This paper presents a switched-capacitor DeltaSigma analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3-1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped switch solves the non-linearity issues of low-voltage transmission gates. The higher flicker noise of nanoscale CMOS technologies is reduced by applying chopping to the first amplifier input pair.

Keywords

CMOS integrated circuits; amplifiers; bootstrap circuits; cascade networks; choppers (circuits); delta-sigma modulation; network topology; aggressive noise-shaping; amplifier input pair chopping; bandwidth 1 MHz; cascade topology; delta-sigma ADC; flicker noise; low-voltage transmission gates; nanoscale CMOS technology; nonlinearity; power 17 mW; size 65 nm; symmetrical bootstrapped switch; voltage 1 V; Bandwidth; CMOS technology; Energy consumption; Filters; Low voltage; Noise reduction; Noise shaping; Signal to noise ratio; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5326016

Filename

5326016