Title :
A 150 MHz CMOS EPLD with μW standby power
Author :
Baucom, Terry ; Allen, Michael
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
The design and performance of a universal 300-gate equivalent CMOS electrically programmable logic device (EPLD) are reported. Innovative circuit techniques were utilized to achieve high performance. The maximum propagation delay in combinatorial mode is 6 ns, while in register mode, the device can operate at frequencies up to 150 MHz. The standby and active ICC is 10 μA and 70 mA, respectively. The device was fabricated with a 1.0-μm double-metal CMOS EPROM process. The die size is 1.95×2.05 mm
Keywords :
CMOS integrated circuits; large scale integration; logic arrays; 1 micron; 1.95 mm; 10 muA; 150 MHz; 2.05 mm; 6 ns; 70 mA; CMOS; EPLD; PLD; circuit techniques; combinatorial mode; die size; double-metal CMOS EPROM process; electrically programmable logic device; programmable logic devices; propagation delay; register mode; standby power; CMOS logic circuits; Clocks; Driver circuits; Feedback; Frequency; Macrocell networks; Pins; Programmable logic devices; Registers; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124845
