Title :
Efficient built-in self-test for video coding cores: A case study on motion estimation computing array
Author :
Huang, Yu-Sheng ; Chen, Chen-Kai ; Hsu, Chun-Lung
Author_Institution :
Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
Motion estimation algorithms are used in various video coding systems. With the advent of VLSI technology, a large collection of processing elements can be assembled to achieve high-speed computation economically. Rather, the problem of testing a VLSI chip begins with introduction of a defect during the design or implementation phases. Therefore, this paper describes a novel testing scheme of motion estimation. The key part of this scheme is to offer high reliability for motion estimation architecture. The experimental result shows the design achieve 100% fault coverage. And, the main advantages of this scheme are minimal performance degradation, small cost of hardware overhead and the benefit of at-speed testing.
Keywords :
VLSI; built-in self test; motion estimation; reliability; video coding; VLSI technology; built-in self-test; high-speed computation; motion estimation computing array; video coding cores; Assembly; Built-in self-test; Computer architecture; Costs; Degradation; Hardware; Motion estimation; Testing; Very large scale integration; Video coding;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746379