Title :
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Author :
Chih-Chun Lee ; Jiang, J.-H.R. ; Chung-Yang Huang ; Mishchenko, A.
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, ..., gn), i.e. f = h(g1, ..., gn). It plays an important role in many aspects of electronic design automation (EDA), ranging from logic synthesis to formal verification. Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper proposes a novel reformulation that extensively exploits the capability of modern satisfiability (SAT) solvers. Thereby, functional dependency is detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The main strengths of the proposed approach include: (1) fast detection of functional dependency with modest memory consumption and thus scalable to large designs, (2) a full capacity to handle a large set of base functions and thus discovering dependency whenever exists, and (3) potential application to large-scale logic optimization and verification reduction. Experimental results show the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS89 and ITC99 benchmark circuits with up to 200 K gates.
Keywords :
Boolean functions; binary decision diagrams; electronic design automation; formal verification; Boolean function; Craig interpolation; ISCAS89 circuits; ITC99 benchmark circuits; binary decision diagrams; electronic design automation; formal verification logic synthesis; functional dependency; interpolation incremental SAT solving; memory consumption; satisfiability solvers; verification reduction; Binary decision diagrams; Boolean functions; Circuit synthesis; Data structures; Electronic design automation and methodology; Explosions; Formal verification; Interpolation; Logic design; Space technology;
Conference_Titel :
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1381-2
DOI :
10.1109/ICCAD.2007.4397270