Title :
BIST approach for testing configurable logic and memory resources in FPGAs
Author :
Zhang, Zhiquan ; Wen, Zhiping ; Chen, Lei ; Zhou, Tao ; Zhang, Fan
Author_Institution :
Beijing Microelectron. Tech.Instn. (BMTI), Beijing
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
This paper presents a built-in self-test (BIST) approach for testing configurable logic and memory resources in Xilinx Virtex FPGAs using hard-macro. The resources under test include the configurable logic blocks (CLBs) and block random access memories (BRAMs) in all of their modes of operation. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults of the logic resources, and completely tests any address and data bus widths of configurable memory resources. Only 37 total test configurations (24 for logic BIST, 13 for RAMs BIST) are required while retrieving the BIST results using scan chain method.
Keywords :
built-in self test; field programmable gate arrays; logic testing; random-access storage; BIST approach; Xilinx Virtex FPGA; block random access memories; built-in self-test approach; configurable logic blocks; configurable logic testing; logic resources; memory resources; multiple stuck-at gate-level faults; scan chain method; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Field programmable gate arrays; Hardware design languages; Logic testing; Programmable logic arrays; Random access memory; Reconfigurable logic;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746383
