• DocumentCode
    2330734
  • Title

    Automated refinement checking of concurrent systems

  • Author

    Kundu, Sudipta ; Lerner, Sorin ; Gupta, Rajesh

  • Author_Institution
    California Univ., La Jolla
  • fYear
    2007
  • fDate
    4-8 Nov. 2007
  • Firstpage
    318
  • Lastpage
    325
  • Abstract
    Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for digital circuits from high level specifications. It can also be used for post-synthesis modification such as in engineering change orders (ECOs). Therefore, checking if a system, modeled as a set of concurrent processes, is a refinement of another is of tremendous value. In this paper, we focus on concurrent systems modeled as communicating sequential processes (CSP) and show their refinements can be validated using insights from translation validation, automated theorem proving and relational approaches to reasoning about programs. The novelty of our approach is that it handles infinite state spaces in a fully automated manner. We have implemented our refinement checking technique and have applied it to a variety of refinements. We present the details of our algorithm and experimental results. As an example, we were able to automatically check an infinite state space buffer refinement that cannot be checked by current state of the art tools such as FDR. We were also able to check the data part of an industrial case study on the EP2 system.
  • Keywords
    communicating sequential processes; concurrency control; formal specification; high level synthesis; reasoning about programs; state-space methods; theorem proving; EP2 system; automated refinement checking; automated theorem proving; communicating sequential processes; concurrent systems; digital circuits; engineering change orders; high level specifications; post-synthesis modification; reasoning about programs; refinement checking technique; state spaces; stepwise refinement; translation validation; Circuit synthesis; Digital circuits; Hardware; Humans; Manuals; Reasoning about programs; Refining; Silicon; Software systems; State-space methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-1381-2
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2007.4397284
  • Filename
    4397284