Design method for monolithic DC-DC converters based on the losses optimization of the power stage

Author

Costa, Vitor ; Santos, Pedro M. ; Borges, Beatriz

Author_Institution

Inst. de Telecomun., Lisbon

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

1872

Lastpage

1875

Abstract

A design method for efficient monolithic hard-switching converters is proposed in this paper. A power loss model of the power stage including the driver circuits is defined. Based on this model and taking as reference the 0.35 mum CMOS technology from AMS a buck converter is designed. For a given set of operating conditions, the power loss model defined permits to optimize the design parameters for the power stage like the gate-driver tapering factor and the width of the power MOSFET. Extracted circuit simulation results of a buck converter design example operating at 100 MHz switching frequency on layout stage are presented.

Keywords

DC-DC power convertors; driver circuits; integrated circuit design; buck converter design; driver circuits; frequency 100 MHz; hard-switching converters; losses optimization; monolithic DC-DC converters; power stage; Buck converters; CMOS technology; Circuit simulation; DC-DC power converters; Design methodology; Design optimization; Driver circuits; MOSFET circuits; Power MOSFET; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746409

Filename

4746409