Design of IEEE1149.1 testing bus controller IP core

The paper describes an original design of IEEE1149.1 testing bus controller IP core using reusable technology. We have designed the structure of IP core according to the function of IEEE1149.1 testing bus controller. Every function module of IP core was explained detailedly in this paper, including interface of microprocessor module, command control module, TMS creation module, TCK creation module and TDO and TDI buffer module. IP core validating method was shown for proving the validity of this design. IEEE1149.1 testing controller IP core was completed on a FPGA chip using HDL. The IP core can complete the JTAG Protocol conversion, increase speed of auto data loading greatly and improve testing efficiency. So it is the core part of boundary scan testing and we have independent Intellectual Property rights.