DocumentCode
2331260
Title
Cachecompress: a novel approach for test data compression with cache for IP embedded cores
Author
Fang, Hao ; Tong, Chenguang ; Yao, Bo ; Song, Xiaodi ; Cheng, Xu
Author_Institution
Peking Univ., Beijing
fYear
2007
fDate
4-8 Nov. 2007
Firstpage
509
Lastpage
512
Abstract
In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending on the number of specified bits, a test data word is either encoded in a single code word or as a lookup in the dictionary. Explicit dictionary initialization is not required since the content of the dictionary is updated during testing. The dictionary itself only contains the most recently used patterns, thus it exhibits a behaviour similar to a cache. Experiments show that our technique achieves higher compression ratio than other recent compression schemes while the dictionary size has been dramatically reduced.
Keywords
cache storage; data compression; dictionaries; encoding; CacheCompress; IP embedded cores; dynamic dictionary; selective encoding; test data compression; Automatic test pattern generation; Circuit testing; Decoding; Dictionaries; Encoding; Microprocessors; Research and development; Test data compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-1381-2
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2007.4397315
Filename
4397315
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