Novel low power full adder cells in 180nm CMOS technology

Author

Wang, Dan ; Yang, Maofeng ; Cheng, Wu ; Guan, Xuguang ; Zhu, Zhangming ; Yang, Yintang

Author_Institution

Inst. of Microelectron., Xidian Univ., Xi´´an, China

fYear

2009

fDate

25-27 May 2009

Firstpage

430

Lastpage

433

Abstract

This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies Gate-Diffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180 nm CMOS technology. In comparison with Static Energy Recovery Full (SERF) adder cell module, the proposed four full adder cells demonstrate their advantages, including lower power consumption, smaller area, and higher speed.

Keywords

CMOS logic circuits; SPICE; adders; logic design; logic gates; low-power electronics; CMOS technology; GDI technique; Hspice simulation; SERF adder cell module; XNOR gate architecture; XOR gate architecture; circuit design; gate-transistor; low power full adder cell; size 180 nm; static energy recovery full adder cell module; Adders; CMOS technology; Circuit simulation; Circuit synthesis; Computer science; Energy consumption; Equations; Logic; Microelectronics; Paper technology; CMOS; Full Adder; Low Power;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4244-2799-4

Electronic_ISBN

978-1-4244-2800-7

Type

conf

DOI

10.1109/ICIEA.2009.5138242

Filename

5138242