DocumentCode
2331271
Title
A hybrid scheme for compacting test responses with unknown values
Author
Chao, Mango C T ; Cheng, Kwang-Ting ; Wang, Seongmoon ; Chakradhar, Srimat T. ; Wei, Wen-Long
Author_Institution
Nat. Chiao Tung Univ., Hsinchu
fYear
2007
fDate
4-8 Nov. 2007
Firstpage
513
Lastpage
519
Abstract
This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking multiple input signature registers (MISR). The proposed scheme guarantees no coverage loss for the modeled faults. The proposed hybrid scheme can also be tuned to observe any user-specified percentage of responses for controlling the coverage loss for un-modeled faults. The experimental results demonstrate that, in comparison with a space compactor or an unknown-blocking MISR alone, the hybrid compaction scheme achieves a lower coverage loss without demanding more test-data volume. In addition, we propose a quantitative approach to estimate the required percentage of observable responses for the proposed scheme, directly based on a test-quality metric of un-modeled faults.
Keywords
automatic test pattern generation; circuit testing; fault diagnosis; logic testing; shift registers; coverage loss; fault model; space compactor; test quality metric; test response compaction; unknown-blocking multiple input signature registers; Automatic test pattern generation; Chaos; Circuit faults; Compaction; Fault detection; Logic; National electric code; Observability; Signal generators; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-1381-2
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2007.4397316
Filename
4397316
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