Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization

Dual V_t assignment and input vector control are two tightly coupled leakage reduction techniques. We study how to apply them effectively to a circuit to minimize the static leakage power. We argue that simply combining them in a serial fashion will not reach their full potential in leakage reduction. To show this, we propose a heuristic algorithm that integrates them into a single optimization loop by assigning the value for primary inputs and V_t for logic gates simultaneously. Our algorithm leverages the fact that both input vector and threshold voltage V_t have great impact on a gate´s leakage at standby mode and avoids to assign a gate both low V_t and input vector that results high leakage. The selection of input vector and the assignment of V_t are integrated seamlessly through the concepts of leakage observability, worst leakage state, and path factor. The proposed algorithm has a low run time complexity and achieves an average 15% leakage reduction on all the ISCAS and MCNC benchmarks over the serial combination of input vector selection and dual V_t assignment.