Implementation of Otsu´s thresholding process based on FPGA

Otsu´s global automatic image thresholding method has been widely employed in various real-time applications. In this paper, an implementation on FPGA (field programmable gate array) using Altera´s Cyclone II series chip for the BCVC (between class variance computation) of Otsu´s method is presented to meet these high speed requirements. The hardware implementation takes advantage of parallel computation capabilities offered by FPGA technology. The proposed architecture employs Altera´s megacore to eliminate the complex divisions and multiplications in the Otsu´s procedure. The FPGA implementation architecture is verified on DE2 board to enable real-time image segmentation, and the experimental results indicate that the system can obtain a good performance of image segmentation.